It is already known to provide reliable storage and retrieval of large amounts of digital data, such as computer data by means of the DDS (Digital Data Storage) format defined in ISO/IEC Standard, 10777:1991 E.
In a DDS read/write mechanism using the format defined in that Standard data are recorded on an elongate recording media, comprising tape coated with a magnetic medium, by a rotating drum carrying one or more electromagnetic heads. The tape is moved by a motor-driven capstan along a path extending between two spools or reels and wrapped partially around the drum. The plane of rotation of the drum is disposed at an angle to the plane of movement of the tape, so that each head traverses the tape along successive tracks extending across the width of the tape at an angle to its centreline, otherwise referred to as helically scanning. The mechanism includes appropriate circuitry for encoding data into signals suitable for recording on tape, including error detection and correction codes, and for conditioning those signals into a form which is optimally matched to the characteristics of the recording media; for data retrieval, additional circuitry is provided for detecting magnetic field variations stored on the tape, deriving corresponding signals, conditioning those signals into a form suitable for subsequent processing, decoding the encoded data, and detecting and correcting errors.
In DDS1 and DDS2, data are recorded at a bit density of approximately 61 kilobits/inch (Kbpi) (equivalent to approximately 24 kilobits/centimeter). At this density a typical DDS tape cartridge can hold up to approximately 8 Gb of data, using the longest practicable tape and techniques such as data compression to maximise the quantity of data the tape can accommodate. In DDS1 and DDS2 devices, the read head is dimensioned so that it reads one bit cell at a time from the tape. The read signal is equalised and in early DDS the equalised channel was a “waveform restoration” or “full response channel” in which the equalised waveform presented to the detector was essentially a replica of the write current waveform. In such systems the detector only needs to decide whether the equalised waveform is greater or less then zero at each bit instant to choose between +1 and −1. The detector may thus comprise a simple threshold detector which employs a slicing technique.
In DDS3 a doubling of bit density was effected and this made it necessary to abandon the simple technique, to achieve reasonable error rates. Attention is directed to WO95/15551, the entire contents of which are incorporated herein by reference, which describes a partial response, maximum likelihood (PRML) detector for retrieving data using a read head which reads two bits at a time. There are various “classes” of partial response; for example a partial response Class I (PR1) duobinary channel applies a (l+D) transform to the input data. Thus the output is a rolling convolution determined by the sum of two input bits. Since the input values are +1, −1, the noiseless outputs are either −2, 0 or +2. It is no longer possible to detect each bit independently because the decisions are recursive, i.e. they depend on previous decisions. This detection and resolution of ambiguities is done by a technique referred to as maximum likelihood sequence detection (MLSD) which may conveniently utilise Viterbi detection. For example, in an ideal noiseless system a sequence of three-level output values 0, 0, 0, −2 is ambiguous until the arrival of the −2 because the initial output values 0 could mean that the pair (+1, −1) or (−1+1) had been received.
Such ambiguities can only be resolved by waiting until a +2 or −2 is received, which will determine whether the previous sequence should run +1, −1, +1, −1, . . . or −1, +1, −1, +1.
The Viterbi detector implements an algorithm which determines the optimum sequence estimation of a finite state process, given a set of noisy observations. The Viterbi algorithm may be described using a trellis diagram which is a time-indexed version of a state diagram.
In the above example, the arrival of the +/−2 means that the trellis branches converge on the same state, thus indicating which of the two alternate candidate paths back through the trellis is most likely; this convergence is referred to as a merge, and the corresponding most likely path is called the survivor path.
In DDS 3, the trellis implements the rules implicit in the partial response and rejects values which violate these rules. For example in a (1+D) convolution, a direct transition between two 2's of opposite sign is not allowed; there must be an odd number of 0's between two 2's of opposite sign and there must be an even number of 0's between two 2's of the same sign. Each node of the PR1 trellis corresponds to a state (i.e. a positive or negative polarisation) at a given time index and each path or branch corresponds to a state transition.
In a Viterbi decoder each path or branch is assigned a weight, referred to as a branch metric, which is a measure of the likelihood of the associated transition, given a noisy observation. The likelihood of a transition is given by a distance measure between the ideal decoder output and the actual received noisy output. Thus the more likely transitions have smaller metrics. For each input the algorithm calculates the branch metrics and recursively computes the lowest metric paths back from time tn to time tn−1. In this step the decisions are used recursively to update the survivor path of the signal, using a process known as add-compare-select (ACS) recursion. The shortest branch to each trellis state is then found from the ACS recursion, and this is called the survivor path. The two candidate paths are stored by the Viterbi decoder and updated at each time interval.
The 8-10 encoding process decrees that the number of consecutive 0's may not exceed 14, and this means that a merge will occur within 15 time intervals. This means that the path memory need only accommodate two alternative candidate paths for 15 bits, after which the survivor path (or output) will be available.
One of the benefits of the Viterbi algorithm in relation to PR1 detection is that, at any time point in the trellis, it is necessary to store at the most only two candidate paths and the two metrics associated with these paths. It will be appreciated that otherwise, in a system which has two states and requires twenty consecutive transitions to be stored, the memory would need to have storage capacity for up to 214 paths and an associated metric for each path. Given that in practice the bit rate is of the order of 100 MHz the computation load means that this would be impractical.
As noted above, in DDS3, instead of using a full response, i.e. equalising all frequencies up to the Nyquist frequency at full amplitude, a partial response is used in which the frequency response is equalised to a partial response target. FIG. 1 of the accompanying drawings shows the frequency response of a typical magnetic recording channel before any equalisation is applied. The frequency response of the recording channel is a function of the frequency responses of the write heads, the magnetic recording media, the read heads, the associated electronic circuitry, and the bit density of recording. FIG. 2 shows several popular partial response equalisation targets for different classes of partial response (PR1 (1+D), PR2 (1+D2), PR4 (1-D2), EPR4 ((1-D) (1+D)2) and Dicode (1-D). It will be seen that the PR1 and PR2 targets both have nulls at the Nyquist frequency, the dicode target has a null at DC, whereas the PR4 and EPR4 have nulls at both frequencies. It should be noted that the frequency axis scaling in the Figures is not related. The scaling between the two depends on the bit density and the number of samples/bit which is 1 bit/sample for this discussion.
In the design of a DDS read circuit, it is desirable to match the recording channel frequency response to the partial response target. For low bit densities typified by DDS ½, the bit frequency would be around 20 in FIG. 1, putting the Nyquist frequency at around 10 (indicated by the label “Low Density”). The portion of the channel response between 0 and 10 resembles the dicode target of FIG. 2 and this was an early favourite. Increasing the bit density moves the Nyquist frequency further out and the channel response requires much less noise enhancing equalisation to match targets like PR4 and EPR4.
In practice, in DDS3 the PR1 target was used, in spite of an apparent mismatch at DC, where the PR1 target is at a maximum but the channel response is at a null. The reason for selecting PR1 is that it is important to ensure that the signal written on tape is DC free, because the read and write circuitry employs rotary transformers to transfer the rotary:stationary interface on the rotary head. Accordingly, the data is encoded using a DC free modulation code, and in DDS3 a DC free 8-10 modulation code is used, as set out in ECMA Standard ECMA-236, the entire contents of which are incorporated herein by reference. Because the 8-10 modulation code has a null at DC, the low frequencies may be equalised down lower than they would be for a code without this property. Accordingly, the PR1 channel does not need to pass DC but can be cut off at the lower edge of the code spectrum, avoiding a lot of low frequency noise enhancement but not all of it. In other words, the system may be designed such that the channel frequency response is matched to the combination, or product, of the PR1 target and the frequency response of the 8-10 modulation.
With regard to equalising to a PR4 target, inspection of FIGS. 1 and 2 will show that, as compared with PR4 at the same bit density, equalisation of the channel response to a PR1 target requires more low frequency boost and less high frequency boost. The Applicants have found that the noise in the channel before equalisation tends to increase with frequency and thus targets which avoid boosting at high frequencies are preferred.
The quasi-integration of the signal required to produce PR1 results in amplification of low frequency noise. After equalisation, the resultant coloured noise can be equivalently characterised in the time domain as being positively correlated, meaning that adjacent noise samples are more likely to have the same sign. By contrast, if the channel was equalised to a PR4 target (which has a null at DC) at the same bit density, the noise in the detector would be negatively correlated as a result of high frequency noise enhancement in the equaliser.
In a PR1 Viterbi detector, the received sequence of samples is compared to all possible noisefree sequences (with values +2, 0, and −2) in the recursive method described above. The detector then selects that noisefree sequence which is closest to the noisy samples read from the detector. Two types of minimum distance error have been categorised. In a type 1 error the sign of a single bit is misread, i.e. +1 read as −1 or −1 read as +1. For this type of error to occur, two consecutive noisy samples must differ from their noisefree values by 2; for example for a +1 to be misread as −1, the detected noisy sequence out of the detector differs from the correct sequence by: . . . 0, 0, −2, −2, 0, 0 (the minus signs change to plus signs for a −1 misread as a +1)
This type of error affects the digital sum variation (DSV) which is the rolling sum of the binary digits.
In a type 2 error, the (+1, −1) pair is mistaken for the pair (−1, +1) or vice versa. This occurs when the detector choice is wrong by;—    . . . 0, 0, −2, 2, 0 (the signs reverse where −1, +1 is mistaken for +1, −1)
This type of error does not affect the DSV.
In white noise, both of these types of error are equally likely to occur. However when the noise is positively correlated, (i.e. greater at low frequencies or “Red noise”) it is more likely that the noise samples will both have the same sign and therefore in positively correlated noise, errors of the first type tend to predominate. Research by the Applicants has shown that, in a study of DDS3 error events, the first type of error tends to occur more than ten times as often as the second.
Thus, the noise in DDS3 recording is positively correlated and is expected to be even more so in DDS4 recording, where the tracks are closer together and the total system noise becomes more dominated by low frequency, adjacent track cross-talk. Cross-talk noise is predominantly low frequency in DDS3 and 4 as the azimuth angle of the head rejects high frequencies (i.e. short wavelength) from adjacent tracks. Furthermore the Applicants have found that one of the main manufacturing challenges in building DDS or other helical scan mechanisms is preventing variation of the width of the tracks written on tape. If this occurs, some written tracks are narrower than others, which reduces the signal and increases adjacent track cross-talk.
In U.S. Pat. No. 4,888,779 there is disclosed a system for improving coding gain in partial response channels, in which the trellis code spectrum is designed to have nulls at frequencies where the channel transfer function has a null, thereby improving the coding gain and reducing the Viterbi detector complexity. The technique is referred to as “matched spectral null” coding or MSN coding. Thus, according to the above teachings, a PR 1 channel of the type used in DDS systems, and which has a null at the Nyquist frequency, should benefit from a modulation code with a null at the Nyquist frequency. If the noise is white, and a sequence detector matched to the code and channel is used, a gain of 3 dB over uncoded is possible.
U.S. Pat. No. 5,910,969, published after the priority date hereof, describes a system in which a special, dual rate, bipolar code is created which has an overall rate of (k/ql) by mapping a length ‘k’ binary sequence into an output sequence of ‘q’ pairs of bipolar words of length ‘l’. The coding constraint on the construction of the code words requires that they are composed of sub-words whose overall block digital sum (BDS). The sub-words are selected by an inner rate q/l code, whilst the order of the sub-words is determined by an outer rate p/q code.
Although there are substantial benefits in such a proposal, that are many instances where it is not practical to construct a dual rate code. Also the code has a stringent constraint on the BDS which is required to be zero over k bits.
One such instance where a dual rate code is impractical is in helical tape storage devices such as DDS devices which employ an existing DC-free code such as the 8-10 DC-free code. DC-free codes have the property that the digital sum variation is strictly bounded to some small value. The code used in DDS1 and DDS2 was originally designed for audio digital audio tape (DAT) devices and it was required to be DC-free so that it could be transmitted by a rotary transformer. In these original DDS schemes, the codes have a maximum of three 0's before the next 1 must be transmitted. This was important to reduce the amount of crosstalk between adjacent left and right tracks, and also to have sufficient density of transitions to assist timing recovery.
In DDS3, the use of partial response maximum likelihood was adopted to recover the increased density of recording. A Viterbi detector was added, but the original audio 8-10 code had not been designed with a 1+D Viterbi decoder in mind. In the original unmodified code, it was possible to have an arbitrarily long run of consecutive 0's out of the 1+D channel, which do not guarantee merges in the Viterbi detector. For this reason, approximately 10 code words out of the 256 were changed to limit the number of consecutive 0's to 14, to guarantee a merge within every 14 bits and therefore to reduce the path length memory required to a corresponding number of bits. The DSV of the DDS3 code is 7 (the difference varies from −3 to +3). In order further to increase the storage density, the Applicants wished to designed a system with a reduced track pitch, but without requiring a change in the 8-10 coding previously adopted.
In the matched spectral null coding techniques described in U.S. Pat. No. 4,888,779, the teaching has been to match the frequency response of the modulation code with that of the selected partial response channel. But in DDS2 and DDS3, the signal had been equalised to a PR 1 response, =which does not have a null at DC as would be required by the teachings of U.S. Pat. No. 4,888,779.
It would therefore appear that the 8-10 DC-free codes used in DDS are ill-suited for the types of time-varying trellis decoders described in U.S. Pat. No. 4,888,779, and that the investment in terms of increased complexity in providing a time-varying trellis decoder would not be merited by a substantial improvement in the bit error rate. On detailed investigation however, the Applicants determined that the particular combination of employing a DC-free code and equalising to a partial response target having a substantial response at DC means that the equalisation step boosts low frequencies. This applies for any partial response target having a polynomial factor of (1+0) but no (1−D) factors. A lot of the low frequency noise enhancement is avoided because it can be at the lower end of the DC-free code spectrum, but not all of it. The quasi-integration of the signal required to equalised to a substantial signal at DC still results in amplification of low frequency noise. As noted above the Applicants thus determined that the coloured noise can be equivalently characterised in the time domain as being positively correlated; this means that adjacent noise samples are more likely to have the same sign. In addition, the Applicants realised that, as the track pitch employed on the helical scan system decreases, the proportion of crosstalk increases. Crosstalk noise is predominantly low frequency as the alternative azimuth of the head/track rejects high frequency crosstalk for adjacent tracks.
Accordingly, by far the most common errors are attributed to positively correlated noise. The Applicants used this analysis to design a time-varying trellis which eliminates cross talk which contributes to a long-term increase in the digital sum variation (DSV). Another important factor is that in a 8-10 code e.g. with a DSV of 7, the low number of states greatly eased implementation of a time-varying trellis decoder. It is important to note that the low rate penalty of the 8-10 code has effectively been dictated by and paid for by the unrelated need to pass the current through a rotary transformer. Also, as noted above the dual rate codes of U.S. Pat. No. 5,910,969 are specially selected to have a BDS of 0 at the end of each block of ‘k’ bits; the DDS 8-10 codes do not have this property as the DSV at the end of each block is merely bounded to be either +1 or −1, and so again the 8-10 codes would not be compatible with a scheme such as that of U.S. Pat. No. 5,910,969.
Without the detailed analysis conducted by the Applicants, the use of a time-varying trellis decoder in a system using a DC-free code in combination with equalising to a target with a full response at DC would appear only to provide marginal improvements in the bit error rate, therefore not appear to be worth the added complexity. However, in practice, the Applicants found that the use of a time-varying trellis to decode data which has been 8-10 encoded, and then equalised to a target with a response at DC such as partial response channels with a (1+D) but no (1-D) factors, may substantially improve the bit error rate by a factor of up to 10 or more.